`include "wrap_FIFO.v"

`timescale 1ns/1ns

module top ();

parameter FIFO_WIDTH = 4;
parameter FIFO_DEPTH = 2;

reg   reset; // async reset, active on 1
reg   clock; // clock for sync
reg   req; // access request
reg   rnw; // rnw=1-read, rnw=0-write
reg   [FIFO_WIDTH-1:0] wr_data;
wire  [FIFO_WIDTH-1:0] rd_data;
wire  fifo_empty;
wire  fifo_full;


initial 
  begin
    $dumpfile ("queue_sync.dump") ;
    $dumpvars (4, top) ;  
  end

initial begin
  clock = 1'b0;
end

// Verilog testbench, simple one

initial begin
   reset = 1'b0;
   #2 reset = 1'b1; 
   #5 reset = 1'b0;
   req = 1'b1;
   rnw = 1'b0; 
   wr_data = 4'hA;
   #1 req = 1'b0;
   
   #10 req = 1'b1;
   rnw = 1'b0;
   wr_data = 4'hC;
   #1 req = 1'b0; 
   
   #10 req = 1'b1;
   rnw = 1'b1;
   #1 req = 1'b0;
   #20
   $finish();   
end

always #5 clock = ~clock;


wrap_FIFO U_WRAP_FIFO(
  .reset(reset),
  .clock(clock),
  .req(req),
  .rnw(rnw),
  .wr_data(wr_data),
  .rd_data(rd_data),
  .fifo_empty(fifo_empty),
  .fifo_full(fifo_full)
);


endmodule