$date
	Wed Mar 26 23:10:18 2008
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module top $end
$var wire 1 ! fifo_empty $end
$var wire 1 " fifo_full $end
$var wire 4 # rd_data[3:0] $end
$var reg 1 $ clock $end
$var reg 1 % req $end
$var reg 1 & reset $end
$var reg 1 ' rnw $end
$var reg 4 ( wr_data[3:0] $end
$scope module U_WRAP_FIFO $end
$var wire 1 $ clock $end
$var wire 1 ! fifo_empty $end
$var wire 1 " fifo_full $end
$var wire 4 ) rd_data[3:0] $end
$var wire 1 % req $end
$var wire 1 & reset $end
$var wire 1 ' rnw $end
$var wire 4 * wr_data[3:0] $end
$var reg 1 + req_sync $end
$var reg 1 , req_sync_latch $end
$var reg 1 - rnw_sync $end
$var reg 1 . rnw_sync_latch $end
$var reg 4 / wr_data_sync[3:0] $end
$scope module U_FIFO $end
$var wire 1 + req $end
$var wire 1 & reset $end
$var wire 1 - rnw $end
$var wire 4 0 wr_data[3:0] $end
$var reg 1 ! fifo_empty $end
$var reg 1 " fifo_full $end
$var reg 32 1 i[31:0] $end
$var reg 4 2 rd_data[3:0] $end
$var reg 4 3 rd_ptr[3:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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bx 0
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$end
#2
1!
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#7
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#8
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#10
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#15
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#18
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#19
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#20
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#25
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#29
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#30
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#35
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#40
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#45
1$