`include "stack.v"

`timescale 1ns/1ns

module top ();

parameter LIFO_WIDTH = 8;
parameter LIFO_DEPTH = 16;

reg   reset; // async reset, active on 1
reg   push; // push
reg   pop; // pop
reg   [LIFO_WIDTH-1:0] push_data;
wire  [LIFO_WIDTH-1:0] pop_data;
wire  stack_empty;
wire  stack_full;


initial 
  begin
    $dumpfile ("stack.dump") ;
    $dumpvars (4, top) ;  
  end


initial 
  begin
   reset = 1'b0;
   push = 1'b0;
   pop = 1'b0;
#2 reset = 1'b1; 
   #5 reset = 1'b0;
   push = 1'b1;
   push_data = 4'hA;
   #1 push = 1'b0;
   
   #10 push = 1'b1;
   push_data = 4'hC;
   #1 push = 1'b0; 
   
   #10 pop = 1'b1;
   #1 pop = 1'b0;
   #10
   $finish();   
  end

LIFO U_LIFO(
  .reset(reset),
  .push(push),
  .pop(pop),
  .push_data(push_data),
  .pop_data(pop_data),
  .stack_empty(stack_empty),
  .stack_full(stack_full)
);


endmodule