$date
	Wed Apr 16 11:47:42 2008
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module top $end
$var wire 8 ! pop_data[7:0] $end
$var wire 1 " stack_empty $end
$var wire 1 # stack_full $end
$var reg 1 $ pop $end
$var reg 1 % push $end
$var reg 8 & push_data[7:0] $end
$var reg 1 ' reset $end
$scope module U_LIFO $end
$var wire 1 $ pop $end
$var wire 1 % push $end
$var wire 8 ( push_data[7:0] $end
$var wire 1 ' reset $end
$var reg 32 ) i[31:0] $end
$var reg 8 * pop_data[7:0] $end
$var reg 1 " stack_empty $end
$var reg 1 # stack_full $end
$var reg 8 + stack_ptr[7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx +
bx *
bx )
bx (
0'
bx &
0%
0$
0#
0"
bx !
$end
#2
1"
b0 +
1'
#7
0"
b10000 )
b1 +
b1010 &
b1010 (
1%
0'
#8
0%
#18
b10000 )
b10 +
b1100 &
b1100 (
1%
#19
0%
#29
b1100 !
b1100 *
b1 +
1$
#30
0$