`include "wrap_FIFO.v"

`timescale 1ns/1ns

module top ();

parameter FIFO_WIDTH = 4;
parameter FIFO_DEPTH = 2;

reg   reset; // async reset, active on 1
reg   clock; // clock for sync
reg   req; // access request
reg   rnw; // rnw=1-read, rnw=0-write
reg   [FIFO_WIDTH-1:0] wr_data;
wire  [FIFO_WIDTH-1:0] rd_data;
wire  fifo_empty;
wire  fifo_full;


initial $teal_top;

initial 
  begin
    $dumpfile ("queue_sync_teal.dump") ;
    $dumpvars (4, top) ;  
  end

reg test_end;
initial begin
  clock = 1'b0;
  test_end = 0;
  wait (test_end);
  $display("[Verilog] Received Exit from Teal");
  $finish();
end


always #5 clock = ~clock;


wrap_FIFO U_WRAP_FIFO(
  .reset(reset),
  .clock(clock),
  .req(req),
  .rnw(rnw),
  .wr_data(wr_data),
  .rd_data(rd_data),
  .fifo_empty(fifo_empty),
  .fifo_full(fifo_full)
);


endmodule