`include "wrap_FIFO_clkdom_val.v"

`timescale 1ns/1ns

module top ();

parameter FIFO_WIDTH = 8;
parameter FIFO_DEPTH = 16;

reg   reset; // async reset, active on 1
reg   clock_wr; // clock for sync write
reg   clock_rd; // clock for sync read
reg   req; // access request
reg   rnw; // rnw=1-read, rnw=0-write
reg   [FIFO_WIDTH-1:0] wr_data;
wire  [FIFO_WIDTH-1:0] rd_data;
wire  fifo_empty;
wire  fifo_full;
wire  rd_data_val;


initial $teal_top;

initial 
  begin
    $dumpfile ("queue_clkdom_val_test.dump") ;
    $dumpvars (4, top) ;  
  end

reg test_end;
initial begin
  clock_wr = 0;
  #4 clock_rd = 0;
  test_end = 0;
  wait (test_end);
  $display("[Verilog] Received Exit from Teal");
  $finish();
end

always #5 clock_wr = ~clock_wr;
always #5 clock_rd = ~clock_rd;


wrap_FIFO U_WRAP_FIFO(
  .reset(reset),
  .clock_wr(clock_wr),
  .clock_rd(clock_rd),
  .req(req),
  .rnw(rnw),
  .wr_data(wr_data),
  .rd_data(rd_data),
  .rd_data_val(rd_data_val),
  .fifo_empty(fifo_empty),
  .fifo_full(fifo_full)
);


endmodule