#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "teal.h"

using namespace teal;


struct thread_context {
  thread_context (const std::string& p) : 
    path(p), log (p), 
    condition_ (new teal::condition("queue_clkdom_val_test"))  {}
  std::string path;
  vout log;
  teal::condition* condition_;
};

void* monitor (void* c) 
{
  thread_context* context = static_cast <thread_context*> (c);
  vreg fifo_full (context->path + ".U_WRAP_FIFO.fifo_full");
  vreg fifo_empty (context->path + ".U_WRAP_FIFO.fifo_empty");
  vreg clock_wr (context->path + ".U_WRAP_FIFO.clock_wr");
  vreg clock_rd (context->path + ".U_WRAP_FIFO.clock_rd");
  condition* my_condition = context->condition_;

  while (1) {
  
    at(posedge(clock_wr));
    if (fifo_full == 1)
       context->log <<  "Fifo is full: " << endm;
    at(posedge(clock_rd));
    if (fifo_empty == 1)
       context->log <<  "Fifo is empty: " << endm;
  }
  return 0;
}


void verification_top ()
{
vreg reset("top.reset");           // async reset, active on 1
vreg clock_wr("top.clock_wr");           // clock, for w synchronization
vreg clock_rd("top.clock_rd");           // clock, for r synchronization
vreg req("top.req");               // access request
vreg rnw("top.rnw");               // rnw=1-read, rnw=0-write
vreg wr_data("top.wr_data");
vreg rd_data("top.rd_data");
vreg rd_data_val("top.rd_data_val");
vreg fifo_empty("top.fifo_empty");
vreg fifo_full("top.fifo_full");

vout log("queue_clkdom_val_test");

log << teal_info << "Start of verification_top" << endm;

// reset sequence
reset = 1;

int reset_count = 1;
for ( int i(0); i < reset_count; i++ ) {
    at (posedge(clock_wr));
    at (posedge(clock_rd));
}

reset = 0;
// end of reset sequence

log << "End of reset sequence" << endm;

thread_context context ("top");
pthread_t monitor_thread = start_thread (monitor, &context, "queue_clkdom_val_monitor");

srand ( time(NULL) );
unsigned int delay = 0;
wr_data = 4;
for (int i(0) ; i<1000 ; i++)
{
   req = 0;
   rnw = (rand() < RAND_MAX/2) ? 0:1;
   if (rnw == 0)
       wr_data = wr_data + 3;
   if ((fifo_full == 1) && (rnw==0))
       continue;
   if ((fifo_empty == 1) && (rnw==1))
       continue;
   delay = rand()%4;
   req = 1;
   for ( int j(0); j < delay; j++) {
     if (rnw==0) 
       at (negedge(clock_wr));
     if (rnw==1)
       at (negedge(clock_rd));
   }
}

stop_thread (monitor_thread);

if (vlog::get().how_many (vlog::error)) {
    log << teal_info << "Test Failed: Contained " << dec << vlog::get().how_many (vlog::error) << " errors." << endm;
}
else {
  log << teal_info << "Test Passed. "  << endm;
}

vreg finish("top.test_end"); 
finish = 1;


}

#include "../teal_hdl_connect.cpp"