`timescale 1ns/1ns

module FIFO(
  reset,
  req,
  rnw,
  wr_data,
  rd_data,
  fifo_empty,
  fifo_full
);

parameter FIFO_WIDTH = 8;
parameter FIFO_DEPTH = 16;

input   reset; // async reset, active on 1
input   req; // access request
input   rnw; // rnw=1-read, rnw=0-write
input   [FIFO_WIDTH-1:0] wr_data;
output  [FIFO_WIDTH-1:0] rd_data;
output  fifo_empty;
output  fifo_full;

// interface
wire   reset;
wire   req; // access request
wire   rnw; // rnw=1-read, rnw=0-write
wire   [FIFO_WIDTH-1:0] wr_data;
reg  [FIFO_WIDTH-1:0] rd_data;
reg  fifo_empty;
reg  fifo_full;

// internals
reg [FIFO_WIDTH-1:0] fifo[FIFO_DEPTH-1:0];  
reg [FIFO_WIDTH-1:0] rd_ptr;
integer i;

always @ (reset or rd_ptr) 
  begin
   if (reset==1) rd_ptr <= 0;
   case (rd_ptr) 
       0: fifo_empty <= 1'b1;
       FIFO_DEPTH: begin
       //              $display("Fifo full\n"); 
                     fifo_full <= 1'b1;
                   end
       default: begin
  //              $display("Default reached\n");
                fifo_empty <= 1'b0;
                fifo_full <= 1'b0;
                end
  endcase
  end



always @ (posedge req) 
  begin
//     $display("Per request display\n");
 //    $display("===================\n");
     
     if ( rnw === 1'b1 ) // read access  
       begin
	 rd_ptr = rd_ptr - 1; 
         rd_data = fifo[rd_ptr];
 //        $display("rd_ptr=%x, rd_data=%x\n",rd_ptr, rd_data);
       end
     else // write access  
       begin
           for (i = FIFO_DEPTH-2; i >= 0 ; i = i - 1)
	   begin
	     fifo[i+1] = fifo[i];
	   end  
  	   fifo[0] = wr_data;  
 //          $display("Inserted wr_data=0x%x, fifo[0]=0x%x\n", wr_data, fifo[0]);
           rd_ptr = rd_ptr + 1'b1;
 //          for (i = 0; i < FIFO_DEPTH ; i = i + 1) $display("fifo[%d]=0x%x, rd_ptr=0x%x\n", i, fifo[i], rd_ptr);
       end
    end




endmodule