`include "queue.v"

`timescale 1ns/1ns

module wrap_FIFO(
  reset,
  clock_wr,
  clock_rd,
  req,
  rnw,
  wr_data,
  rd_data,
  fifo_empty,
  fifo_full
);

parameter FIFO_WIDTH = 8;
parameter FIFO_DEPTH = 16;

input   reset; // async reset, active on 1
input   clock_wr; // clock for write synchronization
input   clock_rd; // clock for read synchronization
input   req; // access request
input   rnw; // rnw=1-read, rnw=0-write
input   [FIFO_WIDTH-1:0] wr_data;
output  [FIFO_WIDTH-1:0] rd_data;
output  fifo_empty;
output  fifo_full;

reg req_sync;
reg req_sync_latch;
reg rnw_sync_latch;
reg rnw_sync;
reg [FIFO_WIDTH-1:0] wr_data_sync;

always @(posedge req)
  begin
    req_sync_latch = req;
    rnw_sync_latch = rnw;
  end

always @(posedge clock_wr)
  begin
    if (req_sync_latch && !rnw_sync_latch)
      begin  
        req_sync = req_sync_latch;
        rnw_sync = rnw_sync_latch;
        wr_data_sync = wr_data;
      end
  end

always @(posedge clock_rd)
  begin
    if (req_sync_latch && rnw_sync_latch)
      begin  
        req_sync = req_sync_latch;
        rnw_sync = rnw_sync_latch;
      end
  end



always @(negedge clock_wr or negedge clock_rd)
  begin
    if (req_sync) begin 
       req_sync = 1'b0;
       req_sync_latch = 1'b0;
    end
  end


FIFO U_FIFO(
  .reset(reset),
  .req(req_sync),
  .rnw(rnw_sync),
  .wr_data(wr_data_sync),
  .rd_data(rd_data),
  .fifo_empty(fifo_empty),
  .fifo_full(fifo_full)
);

endmodule