$date
	Wed Apr  2 12:35:35 2008
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module top $end
$var wire 1 ! fifo_empty $end
$var wire 1 " fifo_full $end
$var wire 8 # rd_data[7:0] $end
$var reg 1 $ clock_rd $end
$var reg 1 % clock_wr $end
$var reg 1 & req $end
$var reg 1 ' reset $end
$var reg 1 ( rnw $end
$var reg 1 ) test_end $end
$var reg 8 * wr_data[7:0] $end
$scope module U_WRAP_FIFO $end
$var wire 1 $ clock_rd $end
$var wire 1 % clock_wr $end
$var wire 1 ! fifo_empty $end
$var wire 1 " fifo_full $end
$var wire 8 + rd_data[7:0] $end
$var wire 1 & req $end
$var wire 1 ' reset $end
$var wire 1 ( rnw $end
$var wire 8 , wr_data[7:0] $end
$var reg 1 - req_sync $end
$var reg 1 . req_sync_latch $end
$var reg 1 / rnw_sync $end
$var reg 1 0 rnw_sync_latch $end
$var reg 8 1 wr_data_sync[7:0] $end
$scope module U_FIFO $end
$var wire 1 - req $end
$var wire 1 ' reset $end
$var wire 1 / rnw $end
$var wire 8 2 wr_data[7:0] $end
$var reg 1 ! fifo_empty $end
$var reg 1 " fifo_full $end
$var reg 32 3 i[31:0] $end
$var reg 8 4 rd_data[7:0] $end
$var reg 8 5 rd_ptr[7:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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$end
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