#include "teal.h"

using namespace teal;


void verification_top ()
{
vreg reset("top.reset");           // async reset, active on 1
vreg clock_wr("top.clock_wr");           // clock, for w synchronization
vreg clock_rd("top.clock_rd");           // clock, for r synchronization
vreg req("top.req");               // access request
vreg rnw("top.rnw");               // rnw=1-read, rnw=0-write
vreg wr_data("top.wr_data");
vreg rd_data("top.rd_data");
vreg fifo_empty("top.fifo_empty");
vreg fifo_full("top.fifo_full");

vout log("queue_clkdom_test");

log << teal_info << "Start of verification_top" << endm;

// reset sequence
reset = 1;

int reset_count = 1;
for ( int i(0); i < reset_count; i++ )
    at (posedge(clock_wr));

reset = 0;
// end of reset sequence

log << "End of reset sequence" << endm;

req = 1;
rnw = 0;  // write, rnw=0
wr_data = 0x4;
int req_count = 1; // 1 tick request
for ( int i(0); i < req_count; i++ )
    at (posedge(clock_wr));
log << "Insert data: " << wr_data << endm;

req = 0;
rnw = 0;
wr_data = 0x7;
at (posedge(clock_wr));

req = 1; // still write, rnw=0
req_count = 1; // 1 tick request
for ( int i(0); i < req_count; i++ )
    at (posedge(clock_wr));
log << "Insert data: " << wr_data << endm;

req = 0;
rnw = 0;
at (posedge(clock_rd));

req = 1;
rnw = 1;  // read, rnw=1 
req_count = 1; // 1 tick request
for ( int i(0); i < req_count; i++ )
    at (posedge(clock_rd));

log << " Read from FIFO:" << rd_data << endm;

if (vlog::get().how_many (vlog::error)) {
    log << teal_info << "Test Failed: Contained " << dec << vlog::get().how_many (vlog::error) << " errors." << endm;
}
else {
  log << teal_info << "Test Passed. "  << endm;
}

vreg finish("top.test_end"); 
finish = 1;


}

#include "../teal_hdl_connect.cpp"