$date
	Wed Mar 26 22:59:06 2008
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module top $end
$var wire 1 ! fifo_empty $end
$var wire 1 " fifo_full $end
$var wire 4 # rd_data[3:0] $end
$var reg 1 $ req $end
$var reg 1 % reset $end
$var reg 1 & rnw $end
$var reg 4 ' wr_data[3:0] $end
$scope module U_FIFO $end
$var wire 1 $ req $end
$var wire 1 % reset $end
$var wire 1 & rnw $end
$var wire 4 ( wr_data[3:0] $end
$var reg 1 ! fifo_empty $end
$var reg 1 " fifo_full $end
$var reg 32 ) i[31:0] $end
$var reg 4 * rd_data[3:0] $end
$var reg 4 + rd_ptr[3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx +
bx *
bx )
bx (
bx '
x&
0%
x$
bx #
0"
0!
$end
#2
1!
b0 +
1%
#7
0!
b1 +
b10 )
b1010 '
b1010 (
0&
1$
0%
#8
0$
#18
1"
b10 +
b10 )
b1100 '
b1100 (
1$
#19
0$
#29
0"
b1010 #
b1010 *
b1 +
1&
1$
#30
0$