`include "first_counter.v"

`timescale 1 ns / 1 ns

module top;
// Declare inputs as regs and outputs as wires
reg clock, reset, enable;
wire [3:0] counter_out;

initial $teal_top;


reg test_end;
initial begin
  test_end = 0;
  wait (test_end);
  $display("[Verilog] Received Exit from Teal");
  $finish();
end


// Initialize all variables
initial begin    
  
//  $dumpfile ("counter.dump") ;
//  $dumpvars (1, top) ;
  clock = 1;

end

// Clock generator
always begin
  #5 clock = ~clock; // Toggle clock every 5 ticks
end

// Connect DUT to test bench
first_counter U_counter (
clock,
reset,
enable,
counter_out
);


endmodule