`include "counter_load.v"

`timescale 1 ns / 1 ns

module top; 
// Declare inputs as regs and outputs as wires
reg clock, reset, enable;
reg load_en;
reg [3:0] load_data;
wire [3:0] counter_out;

initial $teal_top;


reg test_end;
initial begin
  test_end = 0;
  wait (test_end);
  $display("[Verilog] Received Exit from Teal");
  $finish();
end


// Initialize all variables
initial begin    
  
  $dumpfile ("counter_load.dump") ;
  $dumpvars (1, top) ;
  clock = 1;

end

// Clock generator
always begin
  #5 clock = ~clock; // Toggle clock every 5 ticks
end

// Connect DUT to test bench
counter_load U_counter (
clock,
reset,
enable,
load_en,
load_data,
counter_out
);


endmodule