$date
	Sat Jan 19 11:16:53 2008
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module top $end
$var wire 4 ! counter_out[3:0] $end
$var reg 1 " clock $end
$var reg 1 # enable $end
$var reg 4 $ load_data[3:0] $end
$var reg 1 % load_en $end
$var reg 1 & reset $end
$var reg 1 ' test_end $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0'
1&
x%
bx $
x#
1"
b0 !
$end
#5
0"
#10
1"
#15
0"
#20
1"
#25
0"
#30
1"
#35
0"
#40
1"
0#
0&
#45
0"
#50
1"
#55
0"
#60
1"
#65
0"
#70
b1 !
1"
1#
#75
0"
#80
b10 !
1"
#85
0"
#90
b11 !
1"
#95
0"
#100
b100 !
1"
#105
0"
#110
b101 !
1"
#115
0"
#120
b110 !
1"
#125
0"
#130
b111 !
1"
#135
0"
#140
b1000 !
1"
#145
0"
#150
b1001 !
1"
#155
0"
#160
b1010 !
1"
#165
0"
#170
b1011 !
1"
#175
0"
#180
b1100 !
1"
#185
0"
#190
b1101 !
1"
#195
0"
#200
b1110 !
1"
#205
0"
#210
b1111 !
1"
#215
0"
#220
b0 !
1"
#225
0"
#230
b1 !
1"
#235
0"
#240
b111 !
1"
b111 $
1%
#245
0"
#250
b1000 !
1"
0%
#255
0"
#260
b1001 !
1"
#265
0"
#270
b1010 !
1"
#275
0"
#280
b1011 !
1"
#285
0"
#290
b1100 !
1"
#295
0"