`include "asyncram.v"


`timescale 1 ns / 1 ns


module top;

   parameter DATA_WIDTH=123;
   parameter ADDR_WIDTH=10;
   parameter RAM_SIZE=313;


   reg cs1, cs2;
   reg rnw;
   reg clk;
   reg test_done;

   wire [DATA_WIDTH-1:0] data;
   reg [DATA_WIDTH-1:0] databus;
   reg [ADDR_WIDTH-1:0] addrbus;

   asyncram U_ram1(data, addrbus, cs1, rnw);
   asyncram U_ram2(data, addrbus, cs2, rnw);

   assign data = rnw ? {DATA_WIDTH{1'bz}} : databus;

   initial begin
      clk = 0;
      test_done = 0; 
      wait  (test_done);
      $display("[Verilog] Received Exit from Teal");
      $finish();
   end

   initial $teal_top;
   
   initial begin
     $dumpfile ("memory_controller_simple.dump") ;
     $dumpvars (1, top) ;
   end
   
   always @(clk)
      #5 clk<=~clk;

endmodule