$date
	Sat Jan 19 14:50:14 2008
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module top $end
$var wire 123 ! data[122:0] $end
$var reg 10 " addrbus[9:0] $end
$var reg 1 # clk $end
$var reg 1 $ cs1 $end
$var reg 1 % cs2 $end
$var reg 123 & databus[122:0] $end
$var reg 1 ' rnw $end
$var reg 1 ( test_done $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0(
1'
bx &
0%
0$
0#
bx "
bz !
$end
#5
1#
#10
0#
#15
1#
#20
0#
#25
bx !
1#
b101 "
b111 &
0'
1$
#30
0#
#35
b0x !
1#
1'
#40
0#