module asyncram
(
  data,
  addr,
  cs,
  rnw
);


   parameter DATA_WIDTH=123;
   parameter ADDR_WIDTH=10;
   parameter RAM_SIZE=313;

   input [ADDR_WIDTH-1:0] addr;
   input cs, rnw;
   inout [DATA_WIDTH-1:0] data;
   
   wire [ADDR_WIDTH-1:0] addr;
   wire cs, rnw;
   wire [DATA_WIDTH-1:0] data;


   reg [DATA_WIDTH-1:0]  membank  [0 : RAM_SIZE-1]; 
   reg [DATA_WIDTH-1:0] int_data;
   
   initial $teal_memory_note (membank);

   always @(cs) begin
      if (cs==1'b1) begin
         if (rnw==1'b1) begin
	    int_data<=membank[addr];
	 end
	 else begin
	    membank[addr]<=data;
	 end
      end
   end

   assign data= cs ? ( rnw ? data_int:{DATA_WIDTH{1'bz}} ) : {DATA_WIDTH{1'bz}};

endmodule