| Digital Circuit Design Using Verilog |
| Tools: |
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| Verilog tutorial: |
Deepak Kumar Verilog tutorial |
| Icarus Verilog (free compiler, simulator and synthesis tool) |
Download it from here |
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| Digital Circuit Design Verification |
| Tools: |
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| CentOS 4.5: |
Download here CentOS 4.5
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| Eclipse C++ IDE |
Download here Eclipse IDE for C/C++
Note: Needs JVM 1.5 + installed |
| Teal ( Verilog - C++ interface library) |
Download here Teal
Note: Make an account. Download the library itself and Teal manual |
| Truss (library with verification classes) |
Download here Truss
Note: Make an account if you didn't do it for Teal. Download the library itself and Truss manual |
| Teal and Truss configuration | How to |
| JVM 1.5 |
JVM 32 bit self-extracting archive (chmod +x <filename> and then run the executable for RPM file)
JVM 64 bit self-extracting archive (chmod +x <filename> and then run the executable for RPM file)
Note:
Please choose one of the self-extracting executables depending
upon your computer (32 or 64 bit). JVM is needed if using Eclipse IDE |
| C/C++ compiler |
Use
gcc that comes with the distribution, please check this option at
instalation time. This compiler is needed in order to use Eclipse IDE
and run tests |
| Waveform viewer |
GTKWave
Dumping waves tutorial |
| Counter dumping waves example |
Counter and counter testbench
Readme file to guide you through the process of dumping waves |
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| Labs |
| Teal counter example |
Files: counter
counter_testbench minimalist
C++ file that replaces monitor functionality
Homework:
1) add checking capabilities to the C++ code
2) write another counter (add load capability for example) and write the C++ file that observes what is happening there |
| Teal counter with load, sepparate thread for monitor/checker |
Files: load counter
load counter_testbench
C++ file with monitor in sepparate thread
waves
log file
Homework:
1) add capability (monitor thread) of detecting passing from 0xfh to 0x0h without signaling an error
2) modify the C++ file (verification_top function) in order to pass the test |
| RAM interface with Teal infrastructure for backdoor access and direct access through transactions |
Files: simple asynchronous DRAM
memory controller testbench
C++ file with simple transaction
waves
log file
Homework:
1)
add monitor capability (in a sepparate thread) that is able to output
in the log the transactions seen on the RAM interface (READ or WRITE)
2)
add checker capability - scoreboard (in a sepparate thread) that is
doing checking the write and read transaction. Also enhance the test
with a bigger number of transactions, to stress monitor and
scoreboard
3) add checker of protocol in another thread. This should check the memory interface protocol |
| Simple async queue and Verilog testbench |
Files: async queue DUT
async queue testbench
waves
Homework:
1) Think at a way to make the testbench more general
2)
add checker capability in the Verilog testbench |
| Simple sync queue and Verilog testbench |
Files: async queue DUT
sync wrapper
sync from async queue Verilog testbench
waves
Homework:
1) Think at a way to make the testbench more general
2)
add checker capability in the Verilog testbench |
Sync queue and simple Teal testbench (single thread)
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Files: async queue DUT
sync wrapper
sync from async testbench
C++ file
waves
log file
Homework:
1) Think at a way to make the C++ code more general (to cover FIFO full, FIFO empty cases)
2)
add monitor capability in a separate thread
3)
add checker capability in a separate thread |
| Clock domain crossing queue |
Files: async queue DUT
2 clocks sync wrapper
testbench
C++ file
waves
Homework:
1) Think at a way to make the C++ code more general (to cover FIFO full, FIFO empty cases)
2)
add monitor capability in a separate thread
3)
add checker capability in a separate thread
4) Play with clocks frequencies to explore the limits of the implementation
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| Clock domain crossing queue with read data valid to validate reads and more complex testbench |
Files: async queue DUT
2 clocks sync wrapper
testbench
C++ file
waves
Homework:
1) Use list from STL to build a scoreboard between the software list and the hardare list (DUT). Make the checkings online
2) Find a method to check that queue_full and queue_empty reported by the design are valid
3)
Build a monitor in a sepparate thread that will make a report on the
number of writes, reads, fifo_full and fifo_empty events. |
| Clock domain crossing queue with read data valid to validate reads and more complex testbench, includes scoreboard |
Files: async queue DUT
2 clocks sync wrapper
testbench
C++ file
waves
log
Homework:
1) The scoreboard is making the test fail. Find the mistake. It is into the DUT or scoreboard? |
| Simple async stack and Verilog testbench | Files: async stack DUT
async stack testbench
waves
Homework:
1) Think at a way to make the testbench more general
2)
add checker capability in the Verilog testbench |
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